Radiation of various types can detrimentally affect the operation of a semiconductor integrated circuit ("IC"). For example, alpha-particle radiation is particularly troublesome for static RAM cells, especially in space applications. Alpha particles can cause the state of a static RAM cell to change in a random, normally undesirable manner.
As static RAM fabrication technology has become more sophisticated and cell dimensions have shrunk, the amount of alpha-particle radiation needed to cause an undesired state change has decreased. Consequently, the radiation sensitivity problem has become more serious.
One category of techniques investigated for reducing the sensitivity of a static RAM cell to radiation entails installing resistors at certain critical points in the cell Generally see Kerns et al, "The Design of Radiation-Hardened ICs for Space: A Compendium of Approaches," Procs IEEE, Nov. 1988, pp. 1470-1509. In particular, see the sections of Kerns et al authored by Rockett, Pridmore, and Berndt.
Capacitive radiation-hardening techniques have also been investigated for MOS static RAM cells. Referring to the drawings, FIG. 1 illustrates a capacitively hardened MOS static RAM cell 10 of conventional design. Static RAM cell 10 centers around cross-connected enhancement-mode N-channel insulated-gate storage field-effect transistors ("FETs") TS1 and TS2 whose sources are connected to a source of a low supply voltage V.sub.LL. Information is stored in static RAM cell 10 at storage nodes 11 and 12 at the drains of FETs TS1 and TS2.
Storage nodes 11 and 12 are coupled through enhancement-mode N-channel insulated-gate access FETs TA1 and TA2 to bit lines B1 and B2. The TA1 and TA2 gate electrodes are connected to a word line W. A load 13 is connected between a source of a high supply voltage V.sub.HH and the TS1 and TS2 drains. Load 13 typically consists of a pair of resistors or a pair of enhancement-mode P-channel insulated-gate FETs.
A pair of capacitors CS1 and CS2 connected between storage nodes 11 and 12, on one hand, and a source of a reference voltage V.sub.FF, on the other hand, provide radiation hardening in cell 10. Capacitors CS1 and CS2 increase the charge stored at nodes 11 and 12. This reduces sensitivity to alpha particles.
Each of capacitors CS1 and CS2 can be formed with a pair of conductive plates sandwiched about a dielectric film. A significant disadvantage of creating capacitors CS1 and CS2 as parallel-plate elements is that the parallel-plate elements occupy a relatively large amount of additional device surface area -- i.e., cell area beyond that occupied by the other elements of the RAM cell.
Alternatively, capacitors CS1 and CS2 can be "junction" capacitors respectively merged with FETs TS1 and TS2. FIG. 2 depicts the junction case in which item 20 is a lightly doped P-type monocrystalline silicon ("monosilicon") semiconductor substrate. Item 21 is an annular oxide-isolation region that defines an active semiconductor island for FET TS1 or TS2. Items 22, 23, and 24 are a gate dielectric layer, a gate electrode, and a pair of oxide spacers. The source for FET TS1 or TS2 consists of a heavily doped main N-type source zone 25M and a lightly doped N-type source extension 25E. The drain consists of a heavily doped main N-type drain zone 26M and a lightly-doped N-type drain extension 26E.
Junction capacitor CS1 or CS2 in FIG. 2 is implemented with moderately doped P-type region 27 situated below the drain. P region 27, which is formed by ion implantation, increases the capacitance at the drain/substrate junction. V.sub.FF is V.sub.LL. An MOS static RAM cell using junction capacitors at the drain nodes to reduce alpha-particle sensitivity can also be formed with the polarities reversed from that shown in FIGS. 1 and 2.
When capacitors CS1 and CS2 are formed as junction elements, the capacitance depends on the chip surface area taken up by P regions 27. That is, increasing the surface area utilized by regions 27 increases the capacitance. The amount of capacitance and, consequently, the level of radiation hardness are relatively small unless the junction-capacitance chip surface area is relatively large. As in the parallel-plate case, this is quite disadvantageous, especially in high-performance space applications where high levels of radiation hardness are needed.